High-density modern semiconductor processes allow designers to shrink what would have been a board-level system into just a single system-on-a-chip (SOC) integrated circuit. As part of this integration, memories that would have existed as separate integrated circuits become embedded memories within a SOC. Although the resulting integration provides a very compact design, the testing of SOCs becomes more and more challenging as the number of integrated components rises. This testing may be classified into two categories, namely that of testing logic and testing memory. Testing embedded memories, such as SRAM's, is more difficult than testing dedicated memory chips because of the relative inaccessibility of the embedded memory. This testing difficulty manifests itself in several ways, such as in memory writing, memory reading, and the memory data path width to the input/output (IO) facilities of the integrated circuit. Should the embedded memories be used as read-only memory (ROM), a user will also need to configure the memories before operation of the integrated circuit. The need to configure and test embedded memories exacerbates the already considerable die area demands of embedded memories.
Conventional approaches to satisfy the need to both configure and test embedded memories have included the use of a row and column signal for each row and column address within each embedded memory within an integrated circuit. Such an approach becomes prohibitive as the number and size of the embedded memories is increased within each integrated circuit. Moreover, as the storage size of embedded memories is increased, the testing time is often increased exponentially.
Accordingly, there is a need in the art for improved testing and configuration capabilities for embedded memories.